1 oct-22-2003 n- & p-channel enhancement mode field effect transistor P2103NV sop-8 niko-sem absolute maximum ratings (t c = 25 c unless otherwise noted) parameters/test conditions symbol n-channel p-channel units drain-source voltage v ds 30 -30 v gate-source voltage v gs 20 20 v t c = 25 c 7 -6 continuous drain current t c = 70 c i d 6 -5 pulsed drain current 1 i dm 28 -24 a t c = 25 c 2 power dissipation t c = 70 c p d 1.3 w junction & storage temperature range t j , t stg -55 to 150 lead temperature ( 1 / 16 ? from case for 10 sec.) t l 275 c thermal resistance ratings thermal resistance symbol typical maximum units junction-to-ambient r ja 62.5 c / w 1 pulse width limited by maximum junction temperature. 2 duty cycle 1% electrical characteristics (t c = 25 c, unless otherwise noted) limits unit parameter symbol test conditions min typ max static v gs = 0v, i d = 250 a drain-source breakdown voltage v (br)dss v gs = 0v, i d = -250 a n-ch p-ch 30 -30 v ds = v gs , i d = 250 a gate threshold voltage v gs(th) v ds = v gs , i d = -250 a n-ch p-ch 0.8 -0.8 1.5 -1.5 2.5 -2.5 v g : gate d : drain s : source product summary v (br)dss r ds(on) i d n-channel 30 21m 7a p-channel -30 35m -6a
2 oct-22-2003 n- & p-channel enhancement mode field effect transistor P2103NV sop-8 niko-sem v ds = 0v, v gs = 20v gate-body leakage i gss v ds = 0v, v gs = 20v n-ch p-ch 100 100 na v ds = 24v, v gs = 0v v ds = -24v, v gs = 0v n-ch p-ch 1 -1 v ds = 20v, v gs = 0v, t j = 55 c zero gate voltage drain current i dss v ds = -20v, v gs = 0v, t j = 55 c n-ch p-ch 10 -10 a v ds = 5v, v gs = 10v on-state drain current 1 i d(on) v ds =-5v, v gs = -10v n-ch p-ch 28 -24 a v gs = 4.5v, i d = 6a v gs = -4.5v, i d = -5a n-ch p-ch 21 44 32 60 v gs = 10v, i d = 7a drain-source on-state resistance 1 r ds(on) v gs = -10v, i d = -6a n-ch p-ch 14 28 21 35 m v ds = 10v, i d = 5a forward transconductance 1 g fs v ds = -10v, i d = -5a n-ch p-ch 8 7 s dynamic input capacitance c iss n-ch p-ch 1700 970 output capacitance c oss n-ch p-ch 380 370 reverse transfer capacitance c rss n-channel v gs = 0v, v ds = 10v, f = 1mhz p-channel v gs = 0v, v ds = -10v, f = 1mhz n-ch p-ch 260 180 pf total gate charge 2 q g n-ch p-ch 40 28 gate-source charge 2 q gs n-ch p-ch 28 6 gate-drain charge 2 q gd n-channel v ds = 0.5v (br)dss , v gs = 10v, i d = 6a p-channel v ds = 0.5v (br)dss , v gs = -10v, i d = -5a n-ch p-ch 12 12 nc
3 oct-22-2003 n- & p-channel enhancement mode field effect transistor P2103NV sop-8 niko-sem turn-on delay time 2 t d(on) n-ch p-ch 20 20 rise time 2 t r n-ch p-ch 10 17 turn-off delay time 2 t d(off) n-ch p-ch 120 160 fall time 2 t f n-channel v ds = 15v i d ? 1a, v gs = 10v, r gen = 6 p-channel v ds = -15v, r l = 1 i d ? -1a, v gs = -10v, r gen = 6 n-ch p-ch 35 75 ns source-drain diode ratin gs and characteristics (t c = 25 c) continuous current i s n-ch p-ch 3 -3 pulsed current 3 i sm n-ch p-ch 6 -6 a i f = 1a, v gs = 0v forward voltage 1 v sd i f = -1a, v gs = 0v n-ch p-ch 1 -1 v i f = 5a, dl f /dt = 100a / s reverse recovery time t rr i f = -5a, dl f /dt = 100a / s n-ch p-ch 15.5 15.5 ns reverse recovery charge q rr n-ch p-ch 7.9 7.9 nc 1 pulse test : pulse width 300 sec, duty cycle 2%. 2 independent of operating temperature. 3 pulse width limited by maximum junction temperature. remark: the product marked with ?P2103NV?, date code or lot #
4 oct-22-2003 n- & p-channel enhancement mode field effect transistor P2103NV sop-8 niko-sem n-channel
5 oct-22-2003 n- & p-channel enhancement mode field effect transistor P2103NV sop-8 niko-sem
6 oct-22-2003 n- & p-channel enhancement mode field effect transistor P2103NV sop-8 niko-sem p-channel
7 oct-22-2003 n- & p-channel enhancement mode field effect transistor P2103NV sop-8 niko-sem
8 oct-22-2003 n- & p-channel enhancement mode field effect transistor P2103NV sop-8 niko-sem soic-8 (d) mechanical data mm mm dimension min. typ. max. dimension min. typ. max. a 4.8 4.9 5.0 h 0.5 0.715 0.83 b 3.8 3.9 4.0 i 0.18 0.254 0.25 c 5.8 6.0 6.2 j 0.22 d 0.38 0.445 0.51 k 0 4 8 e 1.27 l f 1.35 1.55 1.75 m g 0.1 0.175 0.25 n
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